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InTheLoop | 07.28.2014

July 28, 2014

Online Timeline Highlights 40 Years of NERSC Achievements

An interactive timeline highlighting milestones, machines and people over NERSC’s 40-year history is now online. The timeline begins with the Atomic Energy Commission’s 1973 finding that fusion energy research would benefit from high performance computing and decision to locate the Controlled Thermonuclear Research Computer Center at Lawrence Livermore National Laboratory (LLNL). The center was renamed the National Magnetic Fusion Energy Computer Center in 1976 and then the National Energy Research Supercomputer Center in 1990, reflecting its broader mission to support research across the Office of Energy Research (now the Office of Science). When the center moved to Berkeley Lab in 1996, it was rechristened the National Energy Research Scientific Computing Center.
 
The timeline was created by the Computing Sciences Communications Group. Drawing on archives from LLNL, Jon Bashor researched and wrote the text and tracked down many of the images. Margie Wylie built out the timeline on the web and Michael Urashka implemented it on NERSC's site. »Visit the NERSC timeline.

Vint Cerf Cites ESnet as Example of Good R&D Investment

Scientific American recently reprinted the July 17 written testimony of Vint Cerf, a member of ESnet's Policy Board, before the U.S. Senate Committee on Commerce, Science, and Transportation. In his testimony Cerf says that the value of investment by the U.S. government in basic and applied research "cannot be overstated." He cites ESnet's role in growing the Internet as an example of benefits of this investment. »Read more.

SC14 Registration Opens, Technical Program Online, and Posters Deadline Approaching

Online registration for the 2014 International Conference on High Performance Computing, Networking, Storage and Analysis, better known as SC14, is now open on the SC14 website. This year's conference will be held Nov. 16-21, 2014, in New Orleans. »Register online.

SC14’s Technical Program is also now live on the website listing panels, research papers, tutorials, and workshops. »Peruse the technical program.

Thursday, July 31, is the SC14 deadline for  poster submissions that display original, unpublished, cutting-edge research and work in progress in high performance computing, storage, networking, algorithms, and applications. »Learn more.

This Week's CS Seminars

»Visit the CS Seminars Calendar

Current State of the Art in Flash Memory and SSD Architecture

Tuesday, July 29, 2:30pm - 3:30pm, Bldg. 50B, Room 4205

Myoungsoo Jung, University of Texas, Dallas

Abstract unavailable.

Omnipresent Ethernet: From Concepts to Products

Wednesday, July 30, 9am - 10:00am, Bldg. 50B, Room 1237 (ESnet NOC), H.323 video: 857381@es.net

Dr. Ashwin Gumaste, Indian Institute of Technology (IIT), Bombay

The talk begins with the clean-slate design problem of the Internet along with current service provider pain-points, focusing on plausible solutions, narrowing to the concept of Omnipresent Ethernet or OE. The OE concept is introduced as next generation carrier-class Internet architecture. OE extends Ethernet for end-to-end provisioning across the LAN, MAN and WAN, using concepts of Carrier Ethernet in conjunction with simple network architectural understanding. The advantages of OE such as low-latency, low energy, small foot print are discussed. OE working is presented especially in conjunction with some of the advances in Carrier Ethernet leading to a Software Defined Network hierarchy. Mapping OE to multiple layers of the protocol stack and some of the base problems that we have considered will also be showcased. A pragmatic 1-micro-second port-to-port supporting 96 Gbps cross-connect Carrier Ethernet Switch Router will be presented. The working, analysis and the development of this architecture is discussed. OE has led to a family of products, conceptualized, designed, prototyped at IIT Bombay and now made available through the Electronics Corporation of India Ltd, ECIL (http://www.ecil.co.in/ECR/ECR.pdf). We will give an overview of these products, how these have been developed, the internal workings of the hardware and software as well as deployments in the some leading networks and data-centers. Some open problems will also be presented.

Everything You Needed to Know about Memory Technology, but Were Afraid to Ask...

Berkeley Lab – Computing Sciences Exascale Seminar Series
Friday, August 1, 2014, 11am - 12:30pm, Bldg. 50A, Room 5132
Daniel Burke, Researcher, Computer Architecture Lab, Lawrence Berkeley National Laboratory

Memory bandwidth is fundamental to HPC performance, yet we need to balance capacity and power requirements.

An exaflop machine is projected to require 200-300 PB/sec while consuming only 2-3 pJ/bit. Current and new technology trends indicate 10pJ/bit in this timeframe, thus fall short by a factor of 3X-4X.

This talk will cover advanced memory technologies (future NVRAM concepts, memory stacks, HMC, HBM) and how they may be best deployed to meet this goal, and implications of their differing physical characteristics.

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