Kathy Yelick Named Leader of BIPS, CRD’s Future Technologies Group
November 1, 2004
Kathy Yelick, a professor of computer science at UC Berkeley with a joint appointment in the Computational Research Division, has been named to lead for the newly established Berkeley Institute of Performance Studies (BIPS). She will also be leading CRD’s Future Technologies Group (FTG). Yelick’s appointment, which includes a leave of absence from her teaching position, officially takes effect Jan. 1, 2005.
The main goal of Yelick’s research is to develop techniques for obtaining high performance on a wide range of computational platforms and to ease the programming effort required to obtain improved performance. She is perhaps best known for her efforts in global address space (GAS) languages, which attempt to present the programmer with a shared memory model for parallel programming. These efforts have led to the design of Unified Parallel C (UPC), which merged some of the ideas from three shared address space dialects of C: Split-C, AC (from IDA), and PCP (from LLNL). In recent years, UPC has gained recognition as an alternative to message passing programming for large- scale machines. Compaq, Sun, Cray, HP, and SGI are implementing UPC, and Yelick is currently leading a large effort at LBNL to implement UPC on Linux clusters and IBM machines and to develop new optimizations. The language provides a uniform programming model for both shared and distributed memory hardware. Read more at <http://upc.lbl.gov/>. She has also worked on other global address space languages such as Titanium, which is based on Java.
Yelick has also done some notable work on single processor optimizations including techniques for automatically optimizing sparse matrix algorithms for memory hierarchies. These efforts are part of an NSF-funded project called BeBOP (Berkeley Benchmarking and Optimization) that is working on methods to take advantage of special structure such as symmetry and triangular solves.
Another area that Yelick has worked on that has led to very interesting results is her research on architectures for memory-intensive applications and in particular the use of mixed logic and DRAM, which avoids the off-chip accesses to DRAM, thereby gaining bandwidth, while lowering latency and energy consumption. In the IRAM project, a joint effort with David Patterson, she developed an architecture to take advantage of this technology. The IRAM processor is a single chip system designed for low power and high performance on multimedia applications and achieves an estimated 6.4 GOP/s in a two-watt design. The IRAM architecture is based on vector instructions, historically reserved for expensive vector supercomputers designed for large-scale scientific and engineering applications.
Yelick earned her bachelor’s (1985), master’s (1985), and Ph.D. (1991) degrees in electrical engineering and computer science from the Massachusetts Institute of Technology. Her research interests include parallel computing, memory hierarchy optimizations, programming languages and compilers. You can read her UC Berkeley Web page at <http://www.cs.berkeley.edu/~yelick/>.
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