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Katherine Yelick

Yelick.jpg
Katherine Yelick , Ph.D.
Associate Lab Director for Computing Sciences
Phone: +1 510 495 2431* (LBNL) | +1 510 642 8900* (UCB)
Fax: +1 510 643 1534
Lawrence Berkeley National Laboratory

* Email for appointments: Lisa Theobald, Assistant Phone: 510.495.2922  |  Email:  LATheobald@lbl.gov

Biographical Sketch

Kathy Yelick is the Associate Laboratory Director for Computing Sciences at Lawrence Berkeley National Laboratory (Berkeley Lab). The Computing Sciences area at Berkeley Lab comprises the National Energy Research Scientific Computing Division (NERSC), the Scientific Networking Division (home to the Energy Sciences Network, ESnet) and the Computational Research Division. Dr. Yelick has been a Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley since 1991 and has held a joint research appointment at Berkeley Lab since 1996. She was leader of the Future Technologies Group from 2005 through 2007 and the NERSC Director from 2008 through 2012. She earned her Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology and is an internationally recognized expert in high performance computing. Her research interests include parallel programming languages, automatic performance tuning, performance analysis, parallel algorithms, and optimizing compilers.

Journal Articles

Jarrod A Chapman, Martin Mascher, Aydin Buluç, Kerrie Barry, Evangelos Georganas, Adam Session, Veronika Strnadova, Jerry Jenkins, Sunish Sehgal, Leonid Oliker, Jeremy Schmutz, Katherine A Yelick, Uwe Scholz, Robbie Waugh, Jesse A Poland, Gary J Muehlbauer, Nils Stein and Daniel S Rokhsar, "A whole-genome shotgun approach for assembling and anchoring the hexaploid bread wheat genome.", Genome Biology, 2015, 16:26, doi: 10.1186/s13059-015-0582-8

Hongzhang Shan, Amir Kamil, Samuel Williams, Yili Zheng, Katherine Yelick, "Evaluation of PGAS Communication Paradigms with Geometric Multigrid", 8th International Conference on Partitioned Global Address Space Programming Models (PGAS), October 2014,

K. Madduri, J. Su, S. Williams, L. Oliker, S. Ethier, K. Yelick, others, "Optimization of Parallel Particle-to-Grid Interpolation on Leading Multicore Platforms", Parallel and Distributed Systems, IEEE Transactions on, 2012, 23:1915--1922,

R. Nishtala, Y. Zheng, P.H. Hargrove, K.A. Yelick, "Tuning collective communication for Partitioned Global Address Space programming models", Parallel Computing, 2011, 37:576--591,

D. Gay, J. Galenson, M. Naik, K. Yelick, "Yada: Straightforward parallel programming", Parallel Computing, 2011, 37:592--609,

S. Williams, L. Oliker, R. Vuduc, J. Shalf, K. Yelick, J. Demmel, "Optimization of sparse matrix--vector multiplication on emerging multicore platforms", Parallel Computing, 2009, 35:178--194,

K. Datta, S. Kamil, S. Williams, L. Oliker, J. Shalf, K. Yelick, "Optimization and performance modeling of stencil computations on modern microprocessors", SIAM review, 2009, 51:129--159,

S. Williams, J. Carter, L. Oliker, J. Shalf, K. Yelick, "Optimization of a lattice boltzmann computation on state-of-the-art multicore platforms", Journal of Parallel and Distributed Computing, 2009, 69:762--777,

J. Gebis, L. Oliker, J. Shalf, S. Williams, K. Yelick, "Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture", Architecture of Computing Systems--ARCS 2009, 2009, 146--158,

S. Williams, J. Carter, L. Oliker, J. Shalf, K. Yelick, others, "Resource-efficient, hierarchical auto-tuning of a hybrid lattice Boltzmann computation on the Cray XT4", Proc. CUG09: Cray User Group meeting, 2009,

K. Yelick, "Technical perspective Abstraction for parallelism", Communications of the ACM, 2009, 52:88--88,

K. Yelick, "Programming models: Opportunities and challenges for scalable applications", Sandia CSRI Workshop on Next-generation scalable applications: When MPI-only is not enough, 2008,

J. Demmel, M. Hoemmen, M. Mohiyuddin, K. Yelick, "Avoiding communication in sparse matrix computations", Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on, 2008, 1--12,

J. Dongarra, R. Graybill, W. Harrod, R. Lucas, E. Lusk, P. Luszczek, J. Mcmahon, A. Snavely, J. Vetter, K. Yelick, others, "DARPA's HPCS program: History, models, tools, languages", Advances in Computers, 2008, 72:1--100,

S. Williams, K. Datta, J. Carter, L. Oliker, J. Shalf, K. Yelick, D. Bailey, "PERI-Auto-tuning memory-intensive kernels for multicore", Journal of Physics: Conference Series, 2008, 125:012038,

J. Su, K. Yelick, "Automatic communication performance debugging in PGAS languages", Languages and Compilers for Parallel Computing, 2008, 232--245,

S. Williams, K. Datta, L. Oliker, J. Carter, J. Shalf, K. Yelick, "Autotuning Memory-Intensive Kernels for Multicore", 2008,

J. Dongarra, R. Graybill, W. Harrod, R. Lucas, E. Lusk, P. Luszczek, J. McMahon, A. Snavely, J. Vetter, K. Yelick, others, "DARPA s HPCS Program: History, Models, Tools, Languages-1 Historical Background", Advances in Computers, 2008, 72:3,

K. Yelick, P. Hilfinger, S. Graham, D. Bonachea, J. Su, A. Kamil, K. Datta, P. Colella, T. Wen, "Parallel languages and compilers: Perspective from the Titanium experience", International Journal of High Performance Computing Applications, 2007, 21:266--290,

Ewing Lusk, Katherine Yelick, "Languages for High-Productivity Computing: The DARPA HPCS Language Project", Parallel Processing Letters, 2007, 17:89--102,

Conference Papers

Evangelos Georganas, Aydın Buluc ̧ Jarrod Chapman, Leonid Oliker, Daniel Rokhsar, Katherine Yelick, "merAligner: A Fully Parallel Sequence Aligner", Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), May 2015,

Evangelos Georganas, Aydın Buluç, Jarrod Chapman, Leonid Oliker, Daniel Rokhsar and Katherine Yelick, "Parallel De Bruijn Graph Construction and Traversal for De Novo Genome Assembly", 26th ACM/IEEE International Conference on High Performance Computing, Networking, Storage and Analysis (“Supercomputing”, SC 2014), New Orleans, LA, USA., November 2014,

Penporn Koanantakool, Katherine Yelick, "A Computation- And Communication-Optimal Parallel Direct 3-Body Algorithm", 26th ACM/IEEE International Conference on High Performance Computing, Networking, Storage and Analysis (“Supercomputing”, SC 2014), New Orleans, LA, USA, November 2014,

M. Driscoll, E. Georganas, P. Koanantakool, E. Solomonik, K. Yelick, "A Communication-Optimal N-Body Algorithm for Direct Interactions", Proceedings of 27th IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2013,

E. Georganas, J. Gonzalez-Dominguez, E. Solomonik, Y. Zheng, J. Tourino, K.A. Yelick, "Communication Avoiding and Overlapping for Numerical Linear Algebra", SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis ("Supercomputing 2012"), November 2012,

S.J. Min, C. Iancu, K. Yelick, "Hierarchical work stealing on manycore clusters", Fifth Conference on Partitioned Global Address Space Programming Models (PGAS11), 2011,

K. Yelick, "Exascale opportunities and challenges", Proceedings of the 20th international symposium on High performance distributed computing, 2011, 1--2,

H. Shan, N.J. Wright, J. Shalf, K. Yelick, M. Wagner, N. Wichmann, "A preliminary evaluation of the hardware acceleration of the cray gemini interconnect for PGAS languages and comparison with MPI", Proceedings of the second international workshop on Performance modeling, benchmarking and simulation of high performance computing systems, 2011, 13--14,

F. Blagojevi\ c, P. Hargrove, C. Iancu, K. Yelick, "Hybrid PGAS runtime support for multicore nodes", Proceedings of the Fourth Conference on Partitioned Global Address Space Programming Model, 2010, 3,

Y. Zheng, F. Blagojevic, D. Bonachea, P.H. Hargrove, S. Hofmeyr, C. Iancu, S.J. Min, K. Yelick, "Getting multicore performance with UPC", SIAM Conference on Parallel Processing for Scientific Computing, Seattle, Washington (February 2010), 2010,

A. Kamil, K. Yelick, "Enforcing textual alignment of collectives using dynamic checks", Languages and Compilers for Parallel Computing, Springer, 2010, 368--382,

Y. Zheng, C. Iancu, P. Hargrove, S.J. Min, K. Yelick, "Extending Unified Parallel C for GPU Computing", SIAM Conf on Parallel Processing for Scientific Computing, 2010,

B. Catanzaro, S. Kamil, Y. Lee, K. Asanovic, J. Demmel, K. Keutzer, J. Shalf, K. Yelick, A. Fox, "SEJITS: Getting productivity and performance with selective embedded JIT specialization", First Workshop on Programmable Models for Emerging Architecture at the 18th International Conference on Parallel Architectures and Compilation Techniques, 2009,

R. Nishtala, K. Yelick, "Optimizing collective communication on multicores", First USENIX Workshop on Hot Topics in Parallelism (HotPar’09), 2009,

M. Mohiyuddin, M. Hoemmen, J. Demmel, K. Yelick, "Minimizing communication in sparse matrix solvers", Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, 2009, 36,

R. Nishtala, P.H. Hargrove, D.O. Bonachea, K.A. Yelick, "Scaling communication-intensive applications on BlueGene/P using one-sided communication and overlap", Parallel \& Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on, 2009, 1--12,

K. Datta, S. Williams, V. Volkov, J. Carter, L. Oliker, J. Shalf, K. Yelick, "Auto-tuning the 27-point stencil for multicore", In Proc. iWAPT2009: The Fourth International Workshop on Automatic Performance Tuning, 2009,

D. Bonachea, P. Hargrove, M. Welcome, K. Yelick, "Porting GASNet to Portals: Partitioned Global Address Space (PGAS) language support for the Cray XT", Cray Users Group, 2009,

F. Blagojevic, C. Iancu, K. Yelick, M. Curtis-Maury, D.S. Nikolopoulos, B. Rose, "Scheduling dynamic parallelism on accelerators", Proceedings of the 6th ACM conference on Computing frontiers, 2009, 161--170,

J. Demmel, M. Hoemmen, M. Mohiyuddin, K. Yelick, "Communication-optimal iterative methods", Journal of Physics: Conference Series, IOP Publishing, 2009, 180:012040,

D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, K. Yelick, "Intelligent RAM (IRAM): Chips that remember and compute", Solid State Circuits Conference, IEEE, 2008,

K. Datta, M. Murphy, V. Volkov, S. Williams, J. Carter, L. Oliker, D. Patterson, J. Shalf, K. Yelick, "Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures", Proceedings of the 2008 ACM/IEEE conference on Supercomputing, 2008, 4,

S. Williams, J. Carter, L. Oliker, J. Shalf, K. Yelick, "Lattice Boltzmann simulation optimization on leading multicore platforms", Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on, 2008, 1--14,

C. Iancu, W. Chen, K. Yelick, "Performance portable optimizations for loops containing communication operations", Proceedings of the 22nd annual international conference on Supercomputing, 2008, 266--276,

K. Yelick, "Programming models for petascale to exascale", Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on, 2008, 1--1,

A. Kamil, K. Yelick, "Hierarchical pointer analysis for distributed programs", Static Analysis Symposium, Springer, 2007, 281--297,

K. Yelick, D. Bonachea, W.Y. Chen, P. Colella, K. Datta, J. Duell, S.L. Graham, P. Hargrove, P. Hilfinger, P. Husbands, others, "Productivity and performance using partitioned global address space languages", Proceedings of the International Conference on Symbolic and Algebraic Computation, 2007, 27:24--32,

A. Buttari, J. Dongarra, P. Husbands, J. Kurzak, K. Yelick, "Multithreading for synchronization tolerance in matrix factorization", Journal of Physics: Conference Series, IOP Publishing, 2007, 78:012028,

P. Husbands, K. Yelick, "Multi-threading and one-sided communication in parallel LU factorization", Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 2007 (SC '07)., 2007, 1--10,

H. Gahvari, M. Hoemmen, J. Demmel, K. Yelick, "Benchmarking sparse matrix-vector multiply in five minutes", SPEC Benchmark Workshop (January 2007), 2007,

W.Y. Chen, D. Bonachea, C. Iancu, K. Yelick, "Automatic nonblocking communication for partitioned global address space programs", Proceedings of the 21st annual International Conference on Supercomputing (SC '07), 2007, 158--167,

Book Chapters

S. Williams, D. Patterson, L. Oliker, J. Shalf, K. Yelick, "The Roofline Model", Performance Tuning of Scientific Applications, (CRC Press: 2010)

Presentation/Talks

K. Yelick, Compiling to avoid communication, Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Pages: 157--158 2012,

K. Yelick, Beyond UPC, Proceedings of the Third Conference on Partitioned Global Address Space Programing Models, Pages: 2 2009,

K. Yelick, Ten ways to waste a parallel computer (Keynote), Proceedings of the the 36th Annual International Symposium on Computer Architecture (ISCA). Austin, TX, USA: ACM, Pages: 1--1 2009,

K. Yelick, Multicore: Fallout From a Computing Evolution (LBNL Summer Lecture Series), 2008,

K. Yelick, Compilation techniques for partitioned global address space languages, 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006, Revised Papers, Lecture Notes in Computer Science, Pages: 1 2007,

K. Yelick, Performance and Productivity Opportunities using Global Address Space Programming Models, 2006,

Reports

Committee on Future Directions for NSF Advanced Computing Infrastructure to Support U.S. Science and Engineering in 2017-2020, Computer Science and Telecommunication William D. Gropp and Robert Harrison, Co-Chairs; Mark R. Abbott; David Arnett; Robert L. Grossman; Peter M. Kogge; Padma Raghavan; Daniel A. Reed; Valerie Taylor; Katherine A. Yelick; Jon Eisenberg; Shenae Bradley., "Future Directions for NSF Advanced Computing Infrastructure to Support U.S. Science and Engineering in 2017-2020, Interim Report", December 1, 2014,

A.A. Kamil, K.A. Yelick, "Hierarchical additions to the SPMD programming model", Technical Report UCB/EECS-2012-20, University of California, Berkeley, 2012,

Saman Amarasinghe, Mary Hall, Richard Lethin, Keshav Pingali, Dan Quinlan, Vivek Sarkar, John Shalf, Robert Lucas, Katherine Yelick, Pavan Balaji, Pedro C. Diniz, Alice Koniges, Marc Snir, Sonia R. Sachs, October 2011., "Exascale Programming Challenges", Report of the 2011 Workshop on Exascale Programming Challenges Marina del Rey, July 27-29, 2011, 2011,

J. Demmel, M. Hoemmen, M. Mohiyuddin, K. Yelick, "Avoiding communication in computing Krylov subspaces", University of California EECS Department Technical Report UCB/EECS-2007-123, 2007,

R. BISWAS, J. DONGARRA, P. PAUL, AW TRIVELPIECE, K. YELICK, "WTEC Panel Report on High-End Computing Research and Development in Japan.", 2007,

Thesis/Dissertations

Auto-tuning stencil codes for cache-based multicore platforms, K. Datta, PhD, 2009,

Others

J. Mellor-Crummey, P. Beckman, J. Dongarra, B. Miller, K. Yelick, Creating Software Technology to Harness the Power of Leadership-class Computing Systems, 2008,

D.H. Bailey, S. Williams, K. Datta, J. Carter, L. Oliker, J. Shalf, K. Yelick, PERI-Auto-tuning Memory Intensive Kernels for Multicore, 2008,

J. Dongarra, R. Graybill, W. Harrod, R. Lucas, E. Lusk, P. Luszczek, J. Mcmahon, A. Snavely, J. Vetter, K. Yelick, others, DARPA's HPCS program: History, models, tools, languages, Advances in Computers, Pages: 1--100 2008,

T. Wen, J. Su, P. Colella, K. Yelick, N. Keen, An adaptive mesh refinement benchmark for modern parallel programming languages, Proceedings of the 2007 ACM/IEEE Conference on Supercomputing (SC '07), Pages: 1--12 2007,

D.H. Bailey, R. Lucas, P. Hovland, B. Norris, K. Yelick, D. Gunter, B. De Supinski, D. Quinlan, P. Worley, J. Vetter, others, Performance engineering: Understanding and improving the performance of large-scale codes, CTWatch Quarterly, 2007,

K. Fisher, B. Meyer, O. Shivers, L. Wall, K. Yelick, Panel: Programming Language Paradigms: Past, Present, and Future, Proceedings of the third ACM SIGPLAN conference on History of programming languages, Pages: 4 2007,

S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, K. Yelick, Scientific computing kernels on the cell processor, International Journal of Parallel Programming, Pages: 263--298 2007,

R. Nishtala, R.W. Vuduc, J.W. Demmel, K.A. Yelick, When cache blocking of sparse matrix vector multiply works and why, Applicable Algebra in Engineering, Communication and Computing, Pages: 297--311 2007,

Shivali Agarwal, Vivek Sarkar, Rajkishore Barik, Rudrapatna K. Shyamasundar, Dan Bonachea, Katherine Yelick, Deadlock-Free Scheduling of X10 Computations with Bounded Resources, Proceedings of the 19th annual ACM Symposium on Parallel Algorithms and Architectures (SPAA), Pages: 229--240 2007,

K. Asanovic, R. Bodik, B.C. Catanzaro, J.J. Gebis, P. Husbands, K. Keutzer, D.A. Patterson, W.L. Plishker, J. Shalf, S.W. Williams, others, The landscape of parallel computing research: A view from berkeley, 2006,

H. Shan, J. Qiang, E. Strohmaier, K. Yelick, Performance Analysis of a High Energy Colliding Beam Simulation Code on Four HPC Architectures, Parallel Processing, 2006. ICPP 2006. International Conference on, Pages: 237--244 2006,

R. Vuduc, J.W. Demmel, K.A. Yelick, S. Kamil, R. Nishtala, B. Lee, Performance optimizations and bounds for sparse matrix-vector multiply, Supercomputing, ACM/IEEE 2002 Conference, Pages: 26--26 2002,