Kathy Yelick holds a joint research appointment at Berkeley Lab and UC Berkeley. She has been a Electrical Engineering and Computer Sciences professor at the UC Berkeley since 1991 and has held a joint research appointment at Berkeley Lab since 1996.
As an associate lab director, she led the Computing Sciences Area from 2010 through December 2019 when she stepped down to concentrate on research and teaching. She is also a strategic advisor on lab-wide initiatives to Berkeley Lab Director Mike Witherell. Prior to that, she was NERSC director from 2008 through 2012 and leader of the NERSC Future Technologies Group from 2005 through 2007. Dr. Yelick earned her Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology and is an internationally recognized expert in high-performance computing. Her research interests include parallel programming languages, automatic performance tuning, performance analysis, parallel algorithms, and optimizing compilers.
She currently serves as UC Berkeley's vice chancellor for research.
Jarrod A Chapman, Martin Mascher, Aydin Buluç, Kerrie Barry, Evangelos Georganas, Adam Session, Veronika Strnadova, Jerry Jenkins, Sunish Sehgal, Leonid Oliker, Jeremy Schmutz, Katherine A Yelick, Uwe Scholz, Robbie Waugh, Jesse A Poland, Gary J Muehlbauer, Nils Stein and Daniel S Rokhsar, "A whole-genome shotgun approach for assembling and anchoring the hexaploid bread wheat genome.", Genome Biology, 2015, 16:26, doi: 10.1186/s13059-015-0582-8
Hongzhang Shan, Amir Kamil, Samuel Williams, Yili Zheng, Katherine Yelick, "Evaluation of PGAS Communication Paradigms with Geometric Multigrid", 8th International Conference on Partitioned Global Address Space Programming Models (PGAS), October 2014,
K. Madduri, J. Su, S. Williams, L. Oliker, S. Ethier, K. Yelick, others, "Optimization of Parallel Particle-to-Grid Interpolation on Leading Multicore Platforms", Parallel and Distributed Systems, IEEE Transactions on, 2012, 23:1915--1922,
R. Nishtala, Y. Zheng, P.H. Hargrove, K.A. Yelick, "Tuning collective communication for Partitioned Global Address Space programming models", Parallel Computing, 2011, 37:576--591,
D. Gay, J. Galenson, M. Naik, K. Yelick, "Yada: Straightforward parallel programming", Parallel Computing, 2011, 37:592--609,
S. Williams, L. Oliker, R. Vuduc, J. Shalf, K. Yelick, J. Demmel, "Optimization of sparse matrix--vector multiplication on emerging multicore platforms", Parallel Computing, 2009, 35:178--194,
K. Datta, S. Kamil, S. Williams, L. Oliker, J. Shalf, K. Yelick, "Optimization and performance modeling of stencil computations on modern microprocessors", SIAM review, 2009, 51:129--159,
J. Gebis, L. Oliker, J. Shalf, S. Williams, K. Yelick, "Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture", Architecture of Computing Systems--ARCS 2009, 2009, 146--158,
S. Williams, J. Carter, L. Oliker, J. Shalf, K. Yelick, others, "Resource-efficient, hierarchical auto-tuning of a hybrid lattice Boltzmann computation on the Cray XT4", Proc. CUG09: Cray User Group meeting, 2009,
K. Yelick, "Technical perspective Abstraction for parallelism", Communications of the ACM, 2009, 52:88--88,
K. Yelick, "Programming models: Opportunities and challenges for scalable applications", Sandia CSRI Workshop on Next-generation scalable applications: When MPI-only is not enough, 2008,
J. Demmel, M. Hoemmen, M. Mohiyuddin, K. Yelick, "Avoiding communication in sparse matrix computations", Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on, 2008, 1--12,
J. Dongarra, R. Graybill, W. Harrod, R. Lucas, E. Lusk, P. Luszczek, J. Mcmahon, A. Snavely, J. Vetter, K. Yelick, others, "DARPA's HPCS program: History, models, tools, languages", Advances in Computers, 2008, 72:1--100,
S. Williams, K. Datta, J. Carter, L. Oliker, J. Shalf, K. Yelick, D. Bailey, "PERI-Auto-tuning memory-intensive kernels for multicore", Journal of Physics: Conference Series, 2008, 125:012038,
J. Su, K. Yelick, "Automatic communication performance debugging in PGAS languages", Languages and Compilers for Parallel Computing, 2008, 232--245,
S. Williams, K. Datta, L. Oliker, J. Carter, J. Shalf, K. Yelick, "Autotuning Memory-Intensive Kernels for Multicore", 2008,
J. Dongarra, R. Graybill, W. Harrod, R. Lucas, E. Lusk, P. Luszczek, J. McMahon, A. Snavely, J. Vetter, K. Yelick, others, "DARPA s HPCS Program: History, Models, Tools, Languages-1 Historical Background", Advances in Computers, 2008, 72:3,
K. Yelick, P. Hilfinger, S. Graham, D. Bonachea, J. Su, A. Kamil, K. Datta, P. Colella, T. Wen, "Parallel languages and compilers: Perspective from the Titanium experience", International Journal of High Performance Computing Applications, 2007, 21:266--290,
Ewing Lusk, Katherine Yelick, "Languages for High-Productivity Computing: The DARPA HPCS Language Project", Parallel Processing Letters, 2007, 17:89--102,
Evangelos Georganas, Aydın Buluc ̧ Jarrod Chapman, Leonid Oliker, Daniel Rokhsar, Katherine Yelick, "merAligner: A Fully Parallel Sequence Aligner", Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), May 2015,
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