Heterogeneous Architectures

Specialization is the most promising technique for continuing to provide the year-on-year performance increases that all users of computing systems have come to expect over the last four decades. Heterogeneous processor accelerators – whether commercial designs (evolutions of GPU or CPU technologies), emerging reconfigurable hardware, or bespoke architectures that are customized for specific science applications – optimize hardware and software for particular tasks or algorithms and enable performance and/or energy efficiency gains that would not be realized using general-purpose approaches. These long-term trends in the underlying hardware technology (driven by physics) are creating daunting challenges for maintaining the productivity and continued performance scaling of high performance computing (HPC) codes on future systems.

At Berkeley Lab, our strategy is to accelerate the assimilation of emerging heterogeneous specialized technologies that extend far beyond GPUs. We use workload analysis to identify bottlenecks and opportunities for targeted acceleration, co-develop (with industry) effective accelerator technologies, and deploy these technologies in the production of effective heterogeneously accelerated platforms that are specialized for mission scientific applications. Our strategy is designed to maximize the impact of these trends on scientific computing. In the longer term, we expect our co-design methodology to be refined enough that domain scientists, application and software technology developers, hardware architects, and industry partnerships will be established as U.S. government best-practice.

Projects

Project 38

Project 38 is a set of vendor-agnostic architectural explorations involving the Department of Defense (DOD), the Department of Energy (DOE) Office of Science, and DOE National Nuclear Security Administration. The near-term goal is to quantify the performance value and identify the potential costs of specific architectural concepts against a limited set of applications of interest to both the DOE and DOD. In the long-term, the project will develop an enduring capability for DOE and DOD to explore architectural innovations and quantify their value jointly. Contact: John Shalf

DFT Beyond Moore’s Law: Extreme Hardware Specialization for the Future of HPC

The project goal is to demonstrate the performance potential of purpose-built architectures as a potential future for HPC applications in the absence of Moore’s Law. Our approach is to reformulate the LS3DF algorithm to make it amenable to specialized hardware and to develop a custom accelerator for Density Functional Theory. The initial design/prototype will target an FPGA, and results will also be projected to an ASIC. Later, we intend to generalize our results to broader implications for DOE HPC workload. The impact of this project is to determine the feasibility of this approach for future DOE HPC. Doru (Thom) Popovici, John Shalf

iARPA AGILE: Advanced Graphic Intelligence Logical Computing Environment

A fundamental rethinking of computer architectures that can revitalize performance growth trends in computing capabilities is long overdue. Currently, there is a renewed interest in developing specialized hardware components. However, this approach will not resolve the fundamental data movement challenges that restrict the historical performance growth trends. The AGILE program will seed a new generation of computers with unprecedented pathways for continuing performance gains for the Intelligence Community. New architectures developed under the AGILE program will be driven by representative data-intensive applications through the co-design process. Co-design is a process for designing computer systems whereby the application requirements influence architecture decisions, and the architecture affects the design of the applications. Contact: George Michelogiannakis

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