Berkeley Lab engages with other national labs, vendors, and the general research community to help define and evaluate technologies that enhance the effectiveness of HPC for scientific research. One of the Lab's current goals is to understand what the computing landscape will look like following the end of Moore’s Law and post-exascale. As scientific applications and workflows look to a future that incorporates increasingly data-intensive methodologies such as machine learning and deep learning, new opportunities for innovations in HPC system architectures that can increase post-exascale computing capabilities are being explored. We are also exploring the application of quantum information science for discoveries in physics, chemistry, biology, and more.
Near term, specializations such as disaggregated architectures that decouple memory from processors and accelerators represent a promising shift that can meet the demands of next-generation workloads by allowing flexible node designs. Further out, we are exploring the potential benefits of semi-custom supercomputing technologies and their application to high-value science problems.
Advanced Technologies Group at NERSC
NERSC's Advanced Technologies Group engages with other national labs, vendors, and the general research community to help define and evaluate technologies that enhance the effectiveness of HPC for scientific research. One of the group's current goals is to understand what the computing landscape will look like following the end of Moore’s Law and post-exascale. Contact: Nick Wright
PINE: Photonic Integrated Networked Energy efficient datacenters
The Photonic Integrated Networked Energy efficient datacenter (PINE) project is part of the Advanced Research Projects Agency-Energy (ARPA-E) ENergy-efficient Light-wave Integrated Technology Enabling Networks that Enhance Data processing (ENLITENED) program.This project makes designing datacenter racks tailored to emerging applications such as machine learning practical and efficient, since the added cost and performance penalty of using existing interconnect technologies would make sure an approach prohibitive. PINE allows compute, memory or storage modules to be flexibly combined through one-model-ﬁts-all embedded photonic connectivity and better utilize distant fine-resources, even individual chips. This approach substantially increases resource utilization in future large-scale heterogeneous systems. In addition, PINE allows system-level network bandwidth to be reconfigured to better match application demands via bandwidth steering implemented using photonic switches. Contact: George Michelogiannakis
Project 38 is a set of vendor-agnostic architectural explorations involving the Department of Defense (DOD), the Department of Energy (DOE) Office of Science, and NNSA (these latter two organizations are referred to below as “DOE”). These explorations are expected to accomplish the following:
- Near-term goal: Quantify the performance value and identify the potential costs of specific architectural concepts against a limited set of applications of interest to both the DOE and DOD.
- Long-term goal: Develop an enduring capability for DOE and DOD to jointly explore architectural innovations and quantify their value.
Read more with the Project 38 Whitepaper. Contact: John Shalf
DFT Beyond Moore’s Law: Extreme Hardware Specialization for the Future of HPC
The project goal is to demonstrate the performance potential of purpose-built architectures as potential future for HPC applications in absence of Moore’s Law. Our approach is to reformulate the LS3DF algorithm to make it amenable to specialized hardware and to develop a custom accelerator for Density Functional Theory. The initial design/prototype will target an FPGA, and results will also be projected to an ASIC. Later, we intend to generalize our results to broader implications for DOE HPC workload. The impact of this project is to determine the feasibility of this approach for future DOE HPC. Contact: Doru (Thom) Popovici, John Shalf
iARPA AGILE: Advanced Graphic Intelligence Logical Computing Environment
A fundamental rethinking of computer architectures that can revitalize performance growth trends in computing capabilities is long overdue. Currently, there is a renewed interest in developing specialized hardware components. However, this approach will not resolve the fundamental data movement challenges that restrict the historical performance growth trends. The AGILE program will seed a new generation of computers with unprecedented pathways for continuing performance gains for the Intelligence Community.
New architectures developed under the AGILE program will be driven by representative data-intensive applications through the co-design process. Co-design is a process for designing computer systems whereby the application requirements influence architecture decisions, and the architecture affects the design of the applications. Contact: George Michelogiannakis
Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure that aims to provide a parameterizable and powerful on-chip network generator for evaluating future high performance computing architectures based on SoC technology. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make functionality extension as easy as possible. Contact: Farzad Fatollahi-Fard