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Frontiers of Computing

Inventing energy-efficient electronics, materials, systems, devices, manufacturing systems, and architectures to continue exponential technology scaling of digital electronics performance and energy efficiency in response to the tapering of Moore’s Law.

Over the last 50 years, advances in silicon lithography have fueled the exponential miniaturization of electronics and underpinned Moore’s Law. This techno-economic model has allowed the technology industry to double the performance and functionality of digital electronics every two years within a fixed cost, power, and area. But as transistors reach the limits of atomic scales and fabrication costs continue to rise, Moore’s Law is beginning to falter and is anticipated to end by 2025.

Heterogeneous Architectures

Neuromorphic Computing

Quantum Computing

Post-Moore Microelectronics

Superconducting Electronics

At Berkeley Lab, our researchers are reimagining what the future of computing will look like after Moore’s Law and anticipating what challenges lie ahead. We are exploring a range of novel opportunities and strategies to continue improving computing performance, functionality, and efficiency, including superconducting electronics, post-CMOS transistors, new physical phenomena (skyrmions), and new models of computation. We are exploring new technologies and computing systems that transcend the performance limitations caused by the tapering of lithographic scaling, including heterogeneous accelerators, neuromorphic computing, and quantum computing.

Our researchers provide modeling capabilities for new materials, hardware design, and evaluation, as well as algorithms and software developments to improve performance, energy efficiency, integration, and scaling. Our algorithms and software work enable emerging science problems, inform hardware designers of computational requirements and options, and adapt to future hardware features.

The introduction of quantum devices requires even more aggressive algorithms and software work, in addition to classical hardware for control and use in hybrid algorithms.