Current global challenges of climate change, the supply chain, and the end of Moore’s Law demand a new approach to developing microchips. To meet this challenge, we’re partnering with leaders from industry, universities, and the Department of Energy national labs to fabricate and test new electronic materials for energy-efficient silicon microchips. We’re also exploring new multifunctional chip designs enabling electronic devices that are smaller and faster yet more energy efficient than current technologies.
Within ten years, we aim to invent new energy-efficient electronics materials systems, devices, manufacturing systems, and architectures to match or exceed historical “Moore’s Law” rates of improvement of digital electronics performance and energy efficiency beyond 2035 - 2040.
The approaching end of traditional CMOS technology scaling that up until now followed Moore's law is coming to an end in the next decade. However, the DOE has come to depend on the rapid, predictable, and cheap scaling of computing performance to meet mission needs for scientific theory, large-scale experiments, and national security. Moving forward, performance scaling of digital computing will need to originate from energy and cost reductions that are a result of novel architectures, devices, manufacturing technologies, and programming models. The deeper issue presented by these changes is the threat to DOE’s mission and the future economic growth of the U.S. computing industry and society as a whole. With the impending end of Moore’s law, it is imperative for the Office of Advanced Scientific Computing Research (ASCR) to develop a balanced research agenda to assess the viability of novel semiconductor technologies and navigate the ensuing challenges. This report identifies four areas and research directions for ASCR and how each can be used to preserve performance scaling of digital computing beyond exascale and after Moore's law ends. Contacts: Dilip Vasudevan, John Shalf, George Michelogiannakis
PARADISE: PostMoore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiment
An increasing number of technologies are being proposed to preserve digital computing performance scaling as the benefits of lithographic scaling begin to wane with the end of Moore’s Law. PARADISE is an open-source, comprehensive methodology to evaluate emerging technologies with a vertical simulation flow from the individual device level up to the architectural level. PARADISE can be extended to incorporate new technologies for which a compact model exists. In addition, PARADISE is modular with well-defined interfaces between the components so that users can replace any tool in the flow with an equivalent, such as commercial synthesis tools. PARADISE will enable the research community to rapidly evaluate the impact of emerging technologies at the architectural level and thus provide the means to select among available technologies and formulate a strategy toward continued digital computing performance scaling. Contact: Dilip Vasudevan
This project aims to make computation in superconducting circuits, circuits that operate around 4K temperatures and have close to zero resistance, as efficient as possible. Many approaches today try to reuse computing architectures (the design of logic gates and circuits) inspired by traditional technologies into superconducting logic. This is not efficient since superconducting circuits are different: accessing memory is very expensive but the circuit itself can operate at hundreds of GHz frequencies. Using this observation, we make use of race logic computation, which is a computing paradigm developed by our collaborators at UC Santa Barbara that encodes information in the temporal domain. We have designed and taped-out large-scale computing accelerators around them, make them easy to use in a system setting, and decide which science applications would most benefit from such an accelerator in order to design accelerators that can one day be adopted in future supercomputing systems. This approach can achieve multiple orders of magnitude improvements in performance per unit power for a class of applications compatible with this computing scheme. Contact: George Michelogiannakis
We are developing scalable simulation tools to enable leadership computing systems to model the physics of emerging post-CMOS microelectronic devices (electronic, nanomagnetic, ferroelectric, nanomechanical, and multiferroic). Currently, there is a ferroelectric phase-field module, a micromagnetics module, and a dynamic EM module coupled with magnetic spin dynamics. We are working to connect the modules in a fully-coupled fashion. The massively parallel software developed under this project aims to incorporate complex physical coupling previously disregarded due to the difficulty in existing numerical solutions, enabling designers to “improvise” their devices. Contact: Dilip Vasudevan